Memory Design Engineer - Signal Integrity/Cadence Virtuoso (4-10 Yrs) Bangalore (Semiconductor/VLSI/EDA)

Excellent Opportunity with MNC Client Bangalore Short Notice Joining preffered - Role: Design/verification of SRAM/RF/CAM custom/compiler memories in 7FF/16FF technologies.
-Responsibilities: Logic verification with ESPCV and custom vectors, powerup/lockup simulation, Signal Integrity analysis, EM/IR analysis, stress test using lib number, - Characterization, block level design analysis, design optimization.
-Skills and experiences needed: EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills.
-Good communication skills. Should be flexible with work and hard working. Should be good in scripting to analysis large data and summarize.

Required Skills : English