Tessolve - Physical Design Engineer - Netlist/PCI-e (3-8 Yrs) Bangalore (Semiconductor/VLSI/EDA)

Hiring for Physical Design Engineers. Exp : 3 to 8 yrs Education Qualification : B.E/B.tech, M.E/ M.tech Roles responsibilities : - Independent planning and execution of Netlist-to-GDSII.
-Full exposure to all aspects of design flows like floorplanning, placement, CTS, routing.
-Well versed with the level timing closure (STA), timing closure methodologies.
-Well aware of place and route methodologies and hands on experience with timing convergence - Work experience in any of PCIe, MIPI, DDRs will be an added advantage.
-Must have experience in working with latest nodes 7nm,14nm

Required Skills : English