DFT Engineer - Verilog/System Verilog (3-12 Yrs) Bangalore/Chennai (Semiconductor/VLSI/EDA)

JD : - Fundamentals of SCAN stuck-at and at-speed techniques.
-Expertise in handling Mentor Graphics EDT logic.
-Knowledge on On chip clock controller (OCC).
-Pattern generation with Mentor Graphics TestKompress Tool.
-Good knowledge in BSCAN operations. Knowleedge in MBIST Operations.
-Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator).
-Excellent track of pattern simulation and coverage analysis (preferred cadence ncsim simulator expert Experience in ATPG, Scan, BIST and Mentor TestKompress.
-Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors.
-Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor TestKompress.
-Experience with the mentor tool sets.

Required Skills : English